order number: mpc991/d semiconductor technical data rev 0, 08/2001 motorola advanced clock drivers device data 270 the mpc991 is a 3.3 v compatible, pll based ecl/pecl clock driver. the fully differential design ensures optimum skew and pll jitter performance. the performance of the mpc991 makes the device ideal for workstation, mainframe computer and telecommunication applica- tions. the mpc991 offers a differential ecl/pecl input for applications which need to lock to an existing clock signal. it also offers a secondary single?ended ecl clock for system test capabilities. ? fully integrated pll ? output frequency up to 400 mhz ? ecl/pecl inputs and outputs ? operates from a 3.3 v supply ? output frequency configurable ? tqfp packaging ? 50 ps cycle?to?cycle jitter the mpc991 offers three banks of outputs which can each be programmed via the the four fsel pins of the device. there are 16 dif ferent output frequency configurations available in the device. the configura- tions include output ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 4:3:1 and 4:3:2. the programming table in this data sheet illustrates the various programming options. the sync output monitors the relationship between the qa and qc output banks. the output pulses per the timing diagrams in this data sheet signal the coincident edges of the two output banks. this feature is useful for non binary relationships between output frequencies (i.e., 3:2 or 4:3 relationships). the sync_sel input toggles the qd outputs between sync signals and extensions to the qc bank of outputs. the mpc991 provides a separate output for the feedback to the pll. this allows for the feedback frequency to be pro- grammed independently of the other outputs allowing for unique input vs output frequency relationships. the fselfb inputs pro- vide 6 different feedback frequencies from the qfb differential output pair. the mpc991 features an external differential ecl/pecl feedback to the pll. this external feedback feature allows the mpc991 to be used as a ?zero? delay buffer. the propagation delay between the input reference and the output is dependent on the input reference frequency. the selection of higher reference frequencies will provide near zero delay through the device. the pll_en, ref_sel and the test_clk input pins provide a means of bypassing the pll and driving the output buffers direct- ly. this allows the user to single step a design during system debug. note that the test_clk input is routed through the divide rs so that depending on the programming several edges on the test_clk input will be needed to get corresponding edge transitions on the outputs. the vco_sel input provides a means of recentering the vco to provide a broader range of vco frequencies for stable pll operation. if the frequency select or the vco_sel pins are changed during operation, a master reset signal must be applied to ensure output synchronization and phase?lock. if the vco is driven beyond its maximum frequency, the vco can outrun the internal dividers when the vco_sel pin is low. this will also prevent the pll from achieving lock. again, a master reset signal will nee d to be applied to allow for phase?lock. the device employs a power?on reset circuit which will ensure output synchronization and pll lock on initial power?up. rev 0 2 low voltage pll clock driver fa suffix 52?lead tqfp package case 848d?03 see upgrade product ? mpc9991
mpc991 motorola advanced clock drivers device data 271 mpc991 figure 1. 52?lead pinout (top view) function table 1 inputs outputs fsel3 fsel2 fsel1 fsel0 qa qb qc 0 0 0 0 2 2 2 0 0 0 1 2 2 4 0 0 1 0 2 4 4 0 0 1 1 2 2 6 0 1 0 0 2 6 6 0 1 0 1 2 4 6 0 1 1 0 2 4 8 0 1 1 1 2 6 8 1 0 0 0 2 2 8 1 0 0 1 2 8 8 1 0 1 0 4 4 6 1 0 1 1 4 6 6 1 1 0 0 4 6 8 1 1 0 1 6 6 8 1 1 1 0 6 8 8 1 1 1 1 8 8 8 2
mpc991 motorola advanced clock drivers device data 272 function table 2 fselfb2 fselfb1 fselfb0 qfb 0 0 0 0 0 0 1 1 0 1 0 1 2 4 6 8 1 1 1 1 0 0 1 1 0 1 0 1 8 16 24 32 function table 3 control pin logic ?0? logic ?1? pll_en enable pll bypass pll vco_sel fvco fvco/2 ref_sel ecl/pecl test_clk mr ? reset outputs sync_sel sync outputs match qc outputs figure 2. mpc991 logic diagram note: ecl_clk, ext_fb have internal pulldowns, while ecl_clk , ext_fb have external pullups to ensure stability under open input conditions. 2
mpc991 motorola advanced clock drivers device data 273 figure 3. timing diagrams 2
mpc991 motorola advanced clock drivers device data 274 ecl dc characteristics (t a = 0 to 70 c, v cca = v cci = v cco = 0 v, gndi = ?3.3 v 5%, note 1.) 0 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit v oh output high voltage ?1.3 ?0.7 ?1.3 ?1.0 ?0.7 ?1.3 ?0.7 v v ol output low voltage ?2.0 ?1.4 ?2.0 ?1.7 ?1.4 ?2.0 ?1.4 v v ih input high voltage ?1.1 ?0.9 ?1.1 ?0.9 ?1.1 ?0.9 v v il input low voltage ?1.8 ?1.5 ?1.8 ?1.5 ?1.8 ?1.5 v v pp minimum input swing 500 500 500 mv v cmr common mode range v cc ?1.3v v cc ?0.5v v cc ?1.3v v cc ?0.5v v cc ?1.3v v cc ?0.5v v i ih input high current 150 150 150 a i gndi power supply current 200 240 200 240 200 240 ma 1. refer to motorola application note an1545/d ? thermal data for mpc clock drivers ? for thermal management guidelines. pecl dc characteristics (t a = 0 to 70 c, v cca = v cci = v cco = 3.3 v 5%, gndi = 0 v, note 2.) 0 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit v oh output high voltage (note 3.) 2.0 2.6 2.0 2.3 2.6 2.3 2.6 v v ol output low voltage (note 3.) 1.3 1.9 1.3 1.6 1.9 1.3 1.9 v v ih input high voltage (note 3.) 2.2 2.4 2.2 2.4 2.2 2.4 v v il input low voltage (note 3.) 1.5 1.8 1.5 1.8 1.5 1.8 v v pp minimum input swing 500 500 500 mv v cmr common mode range v cc ?1.3v v cc ?0.5v v cc ?1.3v v cc ?0.5v v cc ?1.3v v cc ?0.5v v i ih input high current 150 150 150 a i gndi power supply current 200 240 200 240 200 240 ma 2. refer to motorola application note an1545/d ? thermal data for mpc clock drivers ? for thermal management guidelines. 3. these values are for v cc = 3.3v. level specifications will vary 1:1 with v cc . ac characteristics (t a = 0 to 70 c, v cca = v cci = v cco = 3.3 v 5%, termination of 50 ? to v cc ? 2.0 v) symbol characteristic min typ max unit condition t r , t f output rise/fall time 0.2 1.0 ns 20% to 80% t pw output duty cycle 47.5 50 52.5 % t os output-to-output skew same frequency different frequencies 150 250 250 350 ps f vco pll vco lock range vco_sel = ?0? vco_sel = ?1? 400 200 800 400 mhz fb 8 to 32 (note 4.) fb 4 to 32 t pd ref to feedback offset 75 250 425 ps f ref = 50mhz (note 5.) f max maximum output frequency qa,qb,qc ( 2) qa,qb,qc ( 4) qa,qb,qc ( 6) qa,qb,qc ( 8) 400 200 133 100 mhz t jitter cycle?to?cycle jitter (peak?to?peak) 50 ps t lock maximum pll lock time 10 ms 4. with vco_sel = ?0?, the pll will be unstable with a 2, 4 and some 6 feedback configurations. with v co_sel = ?1?, the pll will be unstable with a 2 feedback ratio. 5. t pd is specified for 50mhz input reference fb 8. the window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods. the t pd does not include jitter. 2
mpc991 motorola advanced clock drivers device data 275 pll input reference characteristics (t a = 0 to 70 c) symbol characteristic min max unit condition t r , t f tclk input rise/falls 3.0 ns f ref reference input frequency feedback divide 6 vco_sel=?0? feedback divide 8 feedback divide 16 feedback divide 24 feedback divide 32 100 50 25 16.67 12.5 125 100 50 33.33 25 mhz vco_sel=?1? feedback divide 4 feedback divide 6 feedback divide 8 feedback divide 16 feedback divide 24 feedback divide 32 50 33.3 25 12.5 8.33 6.25 100 66.67 50 25 16.67 12.5 f refdc reference input duty cycle 25 75 % applications information power supply filtering the mpc991 provides a separate power supply for the internal pll of the device. the purpose of this design technique is to allow the user to filter externally generated system noise from the internal, relatively sensitive analog pll. figure 4 illustrates a suggested power supply filter using an lc filter network. the inductor value should be choosen to maximize the ac filter impedance while maintaining a low dc resistance. an inductor with a maximum dc series resistance of 5 ? should be used. the parallel capacitor combination on the v cca pin ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. figure 4. power supply filter ? 2
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